Dynamic random access memory (DRAM) is utilized in numerous electronic systems. A continuing goal is to increase the level of integration, with a corresponding goal to decrease the size of memory devices. As the design rule of memory devices decreases, channel doping within transistors associated with memory increases to alleviate short channel effects. However, the increased channel doping can cause increased leakage at junctions, which can render it increasingly difficult to obtain sufficient data retention time within the memory devices.
One approach being considered for reducing leakage at junctions is to utilize partially-insulated transistors, and more specifically to utilize partial SOI to alleviate leakage at source/drain junctions. It would be desirable to develop economical methods for incorporating such approach into the fabrication of memory devices. Accordingly, it would be desirable to develop new methods for incorporating partial SOI into memory constructions. It would also be desirable to develop improved memory constructions containing partial SOI.
Although the invention was motivated, at least in part, by a desire to improve memory constructions (such as, for example, DRAM constructions), it is to be understood that the invention described herein can have additional applications besides utilization for memory constructions, and accordingly that the invention is to be limited only by the claims that follow.